Beyond CPU CoresA Deep Dive into AMD EPYC 9555 vs. Intel Xeon 6767P for NVIDIA H200 AI Infrastructure on VMware vSphere 8Understanding PCIe Gen5 Topology, NUMA Locality, Memory Bandwidth, IOMMU, NVL

Understanding PCIe Gen5 Topology, NUMA Locality, Memory Bandwidth, IOMMU, NVIDIA vGPU, and the Architectural Trade-offs Behind GPU-Accelerated Virtualization

Technical Architecture Deep Dive | VMware vSphere 8 | AMD EPYC 9005 | Intel Xeon 6 | NVIDIA H200 NVL

1. Introduction: Why CPU Selection Still Matters in GPU-Accelerated AI Infrastructure

The rapid adoption of large language models, generative AI, retrieval-augmented generation (RAG), and GPU-accelerated analytics has fundamentally changed how enterprise virtualization platforms are designed. Traditional VMware planning focused on CPU consolidation, memory capacity, storage latency, and network throughput. GPU-accelerated AI infrastructure adds the relationship between the CPU, PCIe fabric, system memory, GPU memory, and virtualization layer.

When deploying NVIDIA H200 accelerators on VMware vSphere 8, the CPU must not be evaluated solely by core count or clock frequency. It is part of a heterogeneous computing architecture. This article compares AMD EPYC 9555 (Zen 5) and Intel Xeon 6767P (Granite Rapids), both with 64 physical cores and 128 threads, while distinguishing theoretical specifications, published CPU benchmarks, and actual AI workload performance.

• How many PCIe Gen5 lanes can the processor expose, and how are GPUs physically connected?

• What is the memory-channel and NUMA topology?

• How do AMD-V, VT-x, IOMMU, and GPU assignment interact?

• Which performance conclusions are supported by benchmarks—and which require workload-specific tests?

2. Architectural Baseline: AMD EPYC 9555 vs. Intel Xeon 6767P

Specification | AMD EPYC 9555 | Intel Xeon 6767P

Microarchitecture | Zen 5 | Granite Rapids

Physical cores / threads | 64 / 128 | 64 / 128

Base / maximum turbo | 3.2 / 4.4 GHz | 2.4 / 3.9 GHz

L3 cache | 256 MB | 336 MB

DDR5 channels | 12 | 8

Standard DDR5 speed | Up to 6400 MT/s | Up to 6400 MT/s

PCIe | Gen5, up to 128 lanes | Gen5, up to 88 lanes

TDP | 360 W | 350 W

Memory technology | RDIMM | RDIMM and MRDIMM

Virtualization | AMD-V / NPT / AMD-Vi | VT-x / EPT / VT-d

AMD offers approximately 45.5% more maximum PCIe lanes and 50% more standard DDR5 channels in this specific comparison. Intel provides a larger L3 cache, MRDIMM support, and integrated acceleration technologies such as AMX. These are platform capabilities—not automatic application-level performance gains.

2.1 Why core counts alone mislead

Two 64-core processors may offer different memory, I/O, cache, and acceleration resources. AI pipelines read from NVMe or networks, preprocess on CPU, stage host memory, transfer over PCIe, execute on the GPU, and return results. A balanced design must evaluate the entire path rather than the processor in isolation.

3. PCIe Gen5: The GPU Connectivity Layer

PCIe Gen5 delivers approximately 3.94 GB/s per lane in each direction at the theoretical payload level, before higher-level overhead. A Gen5 x16 link is approximately 63 GB/s each way. Actual application throughput is lower and depends on protocol, platform, device, and transfer pattern.

Example device | Lane demand

H200 GPUs × 4 | 64 (4 × x16)

High-speed NIC | 16 (x16)

NVMe × 4 | 16 (4 × x4)

Additional NIC | 16 (x16)

Illustrative total | 112

This illustrative budget demonstrates the importance of lane capacity, not a claim that Intel cannot support four GPUs. Multi-socket boards, PCIe switches, risers, and vendor wiring change the usable topology. A switch can add downstream ports but shares upstream bandwidth. PCIe lane count does not equal guaranteed GPU throughput.

CPU Socket 0 -> PCIe root complex -> H200 A / H200 B / NIC

CPU Socket 1 -> PCIe root complex -> H200 C / H200 D / NVMe

A GPU’s PCIe root complex, the CPU socket that owns it, and the local memory domain are fundamental to latency-sensitive design. Review motherboard schematics and the server vendor’s validated GPU configuration rather than relying solely on processor specification sheets.

4. NUMA Architecture: The Hidden Performance Variable

Non-Uniform Memory Access (NUMA) means each CPU socket has locally attached memory. Remote memory access generally has different latency and bandwidth characteristics because traffic traverses a socket interconnect. GPU-backed VMs can introduce avoidable cross-socket traffic if CPU execution, host-memory staging, NIC placement, and GPU location are poorly aligned.

NUMA 0: CPU 0 + local DDR5 + GPU 0/1 + NIC

<---- inter-socket fabric ---->

NUMA 1: CPU 1 + local DDR5 + GPU 2/3 + NVMe

• CPU preprocessing and tokenization can become memory intensive.

• Host-to-device transfers often involve pinned system-memory buffers.

• NIC and NVMe placement can introduce cross-socket traffic.

• Multiple tenants can compete for CPU and memory bandwidth within a NUMA node.

ESXi uses NUMA-aware scheduling, but locality must be measured. Check VM vCPU count, vNUMA exposure, memory reservation requirements, PCIe device placement, and CPU Ready / Co-Stop. Manual CPU affinity is not a universal optimization and can reduce scheduler flexibility.

5. Memory Architecture: DDR5 Channels and Bandwidth

At DDR5-6400, one 64-bit channel has a theoretical bandwidth of 6400 million transfers per second × 8 bytes = 51.2 GB/s. At equal data rates, 12 channels provide 614.4 GB/s theoretical aggregate bandwidth, versus 409.6 GB/s across eight channels. These figures are not STREAM measurements or application throughput.

Theoretical DDR5-6400 | AMD EPYC 9555 | Intel Xeon 6767P

Channels | 12 | 8

Per-channel theoretical | 51.2 GB/s | 51.2 GB/s

Aggregate theoretical | 614.4 GB/s | 409.6 GB/s

Real performance depends on DIMM population, speed, rank, memory controllers, NUMA locality, firmware, and workload access patterns. Intel MRDIMM can operate at higher supported transfer rates, so channel count alone cannot prove superior real-world memory performance.

H200 high-bandwidth GPU memory does not eliminate host-memory requirements: tokenization, decompression, retrieval, batching, data staging, networking, and model loading can consume considerable CPU and DDR5 bandwidth. GPU-resident compute workloads may see little CPU-platform difference after weights and data are resident on the GPU.

6. AMD-V, Intel VT-x, and Nested Address Translation

AMD-V (SVM) and Intel VT-x provide hardware-assisted guest execution. AMD Nested Page Tables (NPT) and Intel Extended Page Tables (EPT) translate guest physical addresses to machine addresses, reducing overhead compared with purely software-maintained translation. Both are mature virtualization mechanisms; AMD-V is not an AMD-exclusive advantage over Intel virtualization.

Guest virtual address -> guest physical address -> NPT/EPT -> machine physical address

7. IOMMU: Secure GPU Device Assignment

AMD-Vi/IOMMU and Intel VT-d support device-oriented DMA address translation and isolation. When a PCIe GPU performs DMA, the IOMMU helps constrain access to authorized host-memory mappings. This is essential for safe PCIe device assignment, although firmware, device behavior, hypervisor implementation, and driver security remain part of the trust model.

H200 DMA request -> IOMMU address translation / permissions -> authorized host RAM

7.1 PCIe passthrough on ESXi

DirectPath I/O assigns a physical PCIe GPU to a guest, which uses the appropriate NVIDIA driver. The entire GPU is dedicated to that VM while assigned. Operational restrictions may apply to migration, suspend/resume, snapshots, and other lifecycle functions depending on the hardware and software combination; always check the applicable support matrix.

8. NVIDIA vGPU: Sharing and Isolation

NVIDIA vGPU presents supported GPU resources to virtual machines through NVIDIA vGPU Manager and supported profiles. Time-sliced vGPU logically shares execution resources, whereas MIG-backed vGPU uses hardware GPU instances for stronger partitioning of supported resources. These mechanisms are not interchangeable; neither guarantees elimination of contention in shared host CPU, RAM, network, and storage.

Example H200 NVL time-sliced profile | Nominal framebuffer | Maximum instances per GPU

H200-141C | 141 GB | 1

H200-70C | 70 GB | 2

H200-35C | 35 GB | 4

H200-28C | 28 GB | 5

H200-17C | 17 GB | 8

H200-14C | 14 GB | 10

Profile availability and placement limits depend on the NVIDIA software release and hypervisor support matrix. Examples of MIG-backed H200 profiles include H200-7-141C, H200-4-71C, H200-3-71C, H200-2-35C, H200-1-35C, and H200-1-18C. These are nominal allocations, not guaranteed performance or service levels.

9. GPU Virtualization Is Not CPU-Vendor-Exclusive

Supported AMD and Intel servers can both run NVIDIA H200 passthrough and vGPU. AMD-V versus VT-x and AMD-Vi versus VT-d are implementation differences, not exclusive capabilities. The relevant purchasing question is which complete server provides the best I/O topology, memory subsystem, throughput, operational support, and economics for the workload.

10. CPU Benchmark Analysis: What SPEC CPU2017 Reveals

SPEC CPU2017 rate metrics measure throughput under concurrent benchmark copies. The previously discussed published two-socket system comparisons report AMD EPYC 9555 results of approximately 1720 SPECrate2017 int_base and 1750 fp_base, against selected Intel Xeon 6767P system results of approximately 1310 int_base and 1440 fp_base. These imply roughly 31.3% and 21.5% higher scores for those selected published systems, respectively.

IMPORTANT: These are different vendor systems, with potentially different compiler flags, firmware, DIMM configurations, and tuning. They are not a controlled CPU-only A/B test, nor evidence of corresponding H200, CUDA, LLM inference, or vGPU performance improvements. Confirm each result against its original SPEC disclosure before external publication.

Selected published metric | AMD 2 × EPYC 9555 | Intel 2 × Xeon 6767P

SPECrate2017 int_base | ~1720 | ~1310

SPECrate2017 fp_base | ~1750 | ~1440

11. Intel Xeon 6767P Advantages Worth Evaluating

• Larger L3 cache (336 MB vs 256 MB) may benefit cache-friendly workloads.

• Intel AMX accelerates supported CPU matrix workloads; its usefulness depends on software adoption.

• MRDIMM support can change achievable memory transfer rates and the bandwidth comparison.

• Platform accelerators such as DSA and QAT may benefit supported applications, but do not automatically accelerate H200-resident inference.

12. What Do We Give Up by Choosing the Compared Intel CPU?

Relative to EPYC 9555, Xeon 6767P offers 40 fewer maximum PCIe lanes per processor and four fewer standard DDR5 memory channels. Selected published SPEC system results are lower, but application-level consequences must be measured. The trade-off is not loss of H200 support, vGPU, passthrough, NVMe, or high-speed networking; these remain possible on compatible Intel platforms.

If the actual server already provides all needed GPU x16 links and storage/NIC connectivity without problematic oversubscription, unused extra AMD lanes may have no immediate performance benefit. Their value may lie primarily in future expansion flexibility. Pricing, support, and validated platform design can change the final decision.

13. VMware ESXi 8 Design Considerations

• Enable the correct CPU virtualization and IOMMU options in BIOS/UEFI.

• Verify Above 4G Decoding and sufficient MMIO resources for large PCIe devices.

• Do not assume SR-IOV is universally required for NVIDIA vGPU.

• Document NUMA, power profile, GPU risers, PCIe routing, and firmware versions.

• Use NVIDIA vGPU Manager and guest drivers in a supported compatibility combination.

• Verify licensing acquisition rather than assuming a running nvidia-gridd service proves licensing.

13.1 Useful diagnostic commands

ESXi: esxcli hardware pci list

ESXi: esxcli hardware cpu global get

ESXi: esxcli hardware memory get

ESXi: lspci

Linux guest: nvidia-smi

Linux guest: nvidia-smi -q

Linux guest: lscpu

Linux guest: numactl --hardware

Linux guest: lspci -nn

Guest-visible PCIe and NUMA topology can be virtualized; verify physical root-complex placement on the host. For NVIDIA licensing, protect client configuration tokens and validate the license status in the guest and license service.

14. Designing a Meaningful AI Benchmark

A credible platform comparison controls GPU model/count, guest OS, NVIDIA driver, CUDA, model architecture, precision, batching, network, storage, and power settings. Record server topology and NUMA placement. Use SPEC CPU2017 for CPU throughput, STREAM for memory bandwidth, CUDA transfer tests for host/device bandwidth, and representative LLM inference tests for the actual service objective.

Measurement | What it tells us

TTFT | Time to first generated token

TPOT | Per-output-token latency

Tokens/s | Generation throughput

Requests/s | Concurrent service capacity

P95/P99 latency | Tail latency under contention

CPU Ready / Co-Stop | Hypervisor scheduling contention

NUMA local/remote | Placement efficiency

PCIe transfer bandwidth | Host-to-device bottleneck potential

GPU-dominated, GPU-resident workloads may show minimal differences between CPU platforms. CPU-heavy preprocessing, high concurrency, network-intensive pipelines, and frequent host/device transfers may be more sensitive to platform architecture. Use the workload to select the benchmark, not the benchmark to justify the platform.

15. Performance Engineering: Common Mistakes

• More PCIe lanes do not automatically make an x16-connected GPU faster.

• More memory channels do not guarantee greater real application throughput.

• Time-sliced vGPU and MIG-backed vGPU are different isolation models.

• Ignoring GPU-to-socket and NIC-to-socket NUMA locality can increase latency.

• SPEC CPU2017 scores do not directly measure NVIDIA H200 inference.

• GPU-assigned VMs may not support every standard VM lifecycle operation.

• Comparing CPUs without complete server platform diagrams hides critical limitations.

16. Conceptual Multi-Tenant Architecture

vCenter Server

|

+-- ESXi Host A -- CPU/NUMA/DDR5/PCIe -- H200 GPUs -- vGPU profiles -- AI VMs

|

+-- ESXi Host B -- CPU/NUMA/DDR5/PCIe -- H200 GPUs -- vGPU profiles -- AI VMs

|

+-- AI service layer: LLM inference / RAG / analytics

This is a conceptual host-local architecture, not cross-host GPU pooling. Every physical GPU remains attached to its own server. Workload placement must respect NVIDIA profile support, physical topology, and operational constraints.

17. Final Architectural Assessment

AMD EPYC 9555 offers a strong balance of PCIe Gen5 connectivity, conventional DDR5 channel capacity, and CPU throughput for GPU-dense VMware infrastructure. Intel Xeon 6767P remains a technically capable alternative with larger cache, MRDIMM support, and integrated accelerators. The best choice depends on validated server topology, workload benchmarks, cost, and operational requirements—not brand preference.

The CPU does not simply execute workloads: it defines much of the architecture surrounding the GPU.

18. Technical References

AMD EPYC 9555 product specifications: https://www.amd.com/en/products/processors/server/epyc/9005-series/amd-epyc-9555.html

Intel Xeon 6767P product specifications: https://www.intel.com/content/www/us/en/products/sku/241845/intel-xeon-6767p-processor-336m-cache-2-40-ghz/specifications.html

SPEC CPU2017 results repository: https://www.spec.org/cpu2017/results/

NVIDIA H200 vGPU profiles: https://docs.nvidia.com/ai-enterprise/release-8/latest/infra-software/vgpu/reference/hopper-h200.html

NVIDIA licensing guide: https://docs.nvidia.com/vgpu/latest/grid-licensing-user-guide/configuring-nls-licensed-client.html

VMware/Broadcom documentation: https://techdocs.broadcom.com/

VMware Compatibility Guide: https://compatibilityguide.broadcom.com/

Editorial note: Benchmark figures and supported vGPU profile combinations should be rechecked against their original disclosures and release-specific support matrices before publication. This article distinguishes processor specifications from measured application performance.